Some known incremental compilation technologies for field programmable gate array (FPGA) designs rely on the placement of at least part of the design to be written out in the form of user assignments following a successful compilation. This procedure is referred to as “back-annotation”. In subsequent compilations, the design is recompiled together with the user assignments in an effort to preserve results and to reduce compilation time. Incremental compilation technologies based on back-annotation, however, are susceptible to data mismatch. Data mismatch may cause back-annotated placement to become unusable. User assignments generated via back-annotation take a simple name-value pair form, with the name denoting a textual identifier of a circuit node and the value indicating a location on the device. For a system designer to be able to reuse one such assignment, the name must refer to a valid node in the current netlist. Unfortunately, a given name often cannot be found in the back-annotated netlist for a number of reasons. First, a node name generation algorithm may be perturbed by even a slight change to the project. Second, optimizations such as physical synthesis often change a netlist significantly. This may cause nodes to be created or deleted during compilation. In a subsequent compilation, these changes may not yet have been reproduced with the assignments that are being applied, or they may not be reproducible at all. With the lack of valid assignments, the system designer may need to recompile a major portion of the design. Third, partial constraints can hurt the quality of results due to the fact that the fitter is restricted from doing its job.
Other known incremental compilation technologies employ a hierarchical flow, referred to as a bottom-up flow, where each block of a design is developed separately and potentially in parallel. The full design is generated by combining the individual blocks together. Since blocks are developed independently without knowledge of other blocks in the bottom-up flow, it is impossible for the system design to carry out global optimizations on the blocks. To facilitate global optimizations between blocks, a designer may be required to manually create timing assignments. This process is referred to as delay budgeting. Delay budgeting may become tedious and time consuming when there are several inter-block paths in a design.
Thus, what is needed is an improved method and apparatus for performing compilation.